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TTTC's
Electronic Broadcasting Service |
6th IEEE
International Workshop on Co-located with the 49th ACM/EDAC/IEEE Design Automation Conference |
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FOR PAPERS |
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Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design – manufacturing interface. A wide range of Design-for-Manufacturability (DFM), Design-for-Yield (DFY) and Design-for-Test (DFT) methodologies and tools are proposed today. Some of these are leveraged during the back-end design stages, and others have post design utilization, from lithography up to 3D integration, wafer sort, packaging, final test and failure analysis. These solutions can dramatically impact the business performance of chip manufacturers. They can also significantly affect ageold chip design flows. Using a DFM/DFY/DFT solution is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop will analyze key trends and challenges in DFM, DFY and DFT methodologies, and provide an opportunity to discuss a range of DFM, DFT and DFY solutions for SoC designs now and in the future, including practical case studies that demonstrate the successes and failures of such solutions. Representative topics include, but are not limited to the following:
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To present at the Workshop, authors are invited to submit unpublished extended abstracts or full papers, 2 to 4 pages in length. Submissions on ambitious works in progress are also encouraged. Each submission should include a short abstract of 50 words, and keywords. The review process is blind. Please do not include author names or affiliations. Proposals for embedded tutorials and panel discussions are also invited. Submit a copy of your paper proposal as a PDF at https://www.easychair.org/conferences/?conf=dfmy2012 The goal of the workshop is to foster unrestricted discussion in the field of designmanufacturing- yield-test interactions. Copies of papers will be provided to attendees in the form of Workshop Notes; however, no proceedings will be published. Therefore, accepted papers can still be submitted to other conferences and journals. |
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Submission deadline: April 22, 2012 (Extended) |
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| Additional Information | |||
General Information
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| Committees | |||
General Chairs R. Aitken, ARM Program Chair Special Topics Publicity Steering Committee |
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more information, visit us on the web at: http://vlsicad.ucsd.edu/DFMY/ |
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| The 6th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and with the IEEE Council on Electronic Design Automation (CEDA). |
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IEEE
Computer Society- Test Technology Technical Council |
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TTTC
CHAIR PAST
CHAIR TTTC
1ST VICE CHAIR SECRETARY ITC GENERAL CHAIR TEST
WEEK COORDINATOR TUTORIALS
AND EDUCATION STANDARDS EUROPE MIDDLE
EAST & AFRICA STANDING
COMMITTEES ELECTRONIC
MEDIA |
PRESIDENT OF BOARD SENIOR
PAST CHAIR TTTC 2ND VICE CHAIR FINANCE IEEE DESIGN & TEST EIC TECHNICAL
MEETINGS TECHNICAL
ACTIVITIES ASIA
& PACIFIC LATIN
AMERICA NORTH
AMERICA COMMUNICATIONS INDUSTRY
ADVISORY BOARD |
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